The present invention concerns the use of cell libraries in the design and fabrication of large scale integrated circuits with the aid of a programmed data processor, hereinafter called compiler, by means of which an operator initially specifies a function and achieves a detailed instruction for the layout of a large scale integrated circuit which implements, in the selected technical realisation, the function which has been specified by the operator. The invention more particularly relates to improved techniques for the scaling of cell parameters in such a library.
The design, checking and testing of large scale integrated circuits is so complex that the use of such a programmed data processor is essential for any normal circuit or function. This is partly because the digital signal processing functions are inherently complicated, partly because the main data processing functions need to be decomposed into simpler functions which are within the library of the processor and partly because considerable computation is required in order to achieve an efficient layout of the network. It will be understood that the result of the computerised design process is a detailed specification defining, in terms of a particular technology, a complex integrated circuit. Such a specification may be regarded as a template for the fabrication of the physical embodiment of the integrated circuit.
Compilers of the kind set forth above are commercially available and have been described in the literature. Reference may be made for example to Rabaey et al. "Cathedral--2: Computer Aided Synthesis of Digital Signal Processing Systems", Proceedings of the IEEE CICC 1987 pages 157-160 (1987), S. G. Smith and R. W. Morgan "High Level DSP ASIC Design Tool", Proceedings Euro--ASIC 1989 pages 117-129, Grenoble, France, January 1989; Hartley et al., "A Digit--Serial Silicon Compiler" Proceedings 25th ACM/IEEE DA Conference pages 646-649, California, June 1988; Proceedings of the 24th Design Automation Conference, Miami, Fla., June 1987; Proceedings of the International Workshop on Logic and Architectural Synthesis for Silicon Compilers, Grenoble, May 1988; Proceedings of the International Conference on Computer Aided Design, Santa Clara, Calif., November 1988; and IEEE Transactions on Computer Aided Design on Integrated Circuits and Systems, Volume CAD-5 Number 4, October 1986.
In the operation of a compiler or other generally similar programmed design tool, the operator generally commences with a specification of the function of, for example, a digital signal processor which is to be realised in the selected technology. The initial specification is normally independent of technology. It may be, for example, in the form of an icon network as discussed in U.S. patent application Ser. No. 425634 filed 23rd October 1989 by Stuart G. Smith et al. The machine proceeds to create a detailed netlist, that is to say a specification of the desired function of the processor in terms of standard components or cells. For this purpose the machine has recourse to a "library" of cells. Such libraries are well known and are commercially available.
An important stage in the synthesis of large scale integrated circuits is optimization under programmed control. This process is normally called netlist optimization. A process of logical synthesis may commence with the original functional statement of the circuit that is to be synthesized and followed with stages of minimization, factorisation and mapping. The last mentioned stage is a synthesis in terms of the basic circuits or cells which are maintained for access in a cell library. Before this stage is implemented the circuit which is to be synthesized is expressed in terms of logic, such as Boolean equations, in a manner which is independent of technology. In other words, it does not express the logic in terms of particular circuits which are dependent upon the choice of fabrication, such as CMOS (Complementary Metal Oxide Semiconductors) technology. The mapping process converts the logical representation which is independent of technology into a form which is dependent upon technology and which has recourse to standard circuits, or cells which are held within the cell library forming part of the data available to the data processor.
The mapping process is determined by algorithms which are generally based on three different strategies. These can be broadly characterised as minimization of area, minimization of total delay and minimization using an area-time objective function.
A variety of techniques for technology mapping have been described in the published literature. For example, one may refer to Keutzer et al., "Dagon: Technology Binding and Local Optimization by DHE Matching", Proceedings of the 24th Design Automation Conference, Miami, Fla., June 1987, pages 341-347; Detjiens et al., "Technology Mapping in MIS", proceedings of ICCAD, Santa Clara, Calif., November 1987, pages 116-119; Hachtel et al., "Techmap: Technology Mapping with Delay and Area Optimization", Proceedings of the International Workshop on Logic and Architectural Synthesis for Silicon Compilers, Grenoble, May 1988; and Jit Sing et al., "Timing Optimization of Combinational Logic", proceedings of ICCAD, Santa Clara, Calif., November 1988, pages 282-285.
The processes of minimization and optimization essentially require the programmed machine to compute such things as the area occupied by a provisional layout of an integrated circuit and to determine, according to certain algorithms, whether a different layout achieves, for example, a smaller area of occupation. Alternatively, a given programme may be arranged to minimize time delays or variations in time delays.
Whatever may be the particular reason for an optimization or minimization routine, the programmed machine has recourse to a multiplicity of cells in the cell library, which defines each cell in terms of function and various time delays relevant to the operation of the cell. These delays are, in general, different in nature and magnitude for each cell.
It is known to characterise silicon cell libraries under so called "standard" conditions using a circuit simulator or by means of empirical determination. The obtaining of performance parameters for each cell in a library is a very time consuming operation. It is normal, as illustrated hereinafter with reference to a few selected cells, to specify the time delays in respect of each output relative to each possible input affecting that output. Where the cell library has, typically, hundreds of different cells, the setting up of the library and the provision of characteristic delays and performance parameters is, as mentioned, extremely time consuming.
In practical circumstances however, the conditions under which the final integrated circuit is to operate or is to be fabricated may be different to those for which the performance of the cells is specified. In particular the operating conditions (such as reference voltages and the mean temperature) or the fabrication process variations may be different. In order to compensate for such changes in conditions, it is possible to apply to all the parameters of the cells in the cell library a common scaling factor so that, for example, where TCHR is a characterised delay under the standard or worst case conditions, then a scale factor (S) would be used to determine the delay under the new conditions, the delay TNEW being equal to TCHR*S. The particular scaling factor employed may be selected from memory in accordance with a menu of selectable conditions, including both standard and non-standard conditions, which are to determine the scaling factor.
However, such a scheme is unsatisfactory, because the results are frequently too conservative, resulting in unnecessary loss of performance in the final circuit, or too optimistic, resulting in for example too small safety margins or unrealizable specifications of performance.